RISC-V Pipeline Simulator
A cycle-accurate, 5-stage pipelined CPU simulator with hazard detection and operand forwarding.
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What it's for
Built for a computer architecture course, the simulator models fetch, decode, execute, memory and write-back as discrete stages, so you can watch a program move through the pipeline one cycle at a time.
It detects data and control hazards, inserts stalls when needed, and forwards operands to keep the pipeline full — the same trade-offs real CPUs make.
How to use it
01
Step through a program
Load a RISC-V binary and advance cycle by cycle, inspecting every register and pipeline latch.
02
Visualize hazards
See exactly where stalls and forwards happen on a per-cycle timeline.
03
Compare designs
Toggle forwarding on and off to measure its impact on cycle count.